Reconfigurable Architecture

In reconfigurable architecture, the lab contributes to “Coarse Grain Reconfigurable Architecture” (CGRA) topic. Most CGRAs composed of reconfigurable ALU arrays and configuration cache to achieve high performance and flexibility. We look into low-power design, cache management and smart control techniques to achieve high performance.

Some of the related publications:

  1. Yoonjin Kim, and Rabi N. Mahapatra, “Reusable Context Pipelining for Low Power Coarse-Grained Reconfigurable Architecture,” in Proc. IEEE/ACM International Parallel & Distributed Processing Symposium (IPDPS), pp. 1-8, April 2008 (Acceptance rate 26%).
  2. Yoonjin Kim, Rabi N. Mahapatra, Ilhyun Park, and Kiyoung Choi, “Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 5, pp.593-603, May 2009.
  3. Yoonjin Kim and Rabi N. Mahapatra, “Hierarchical Reconfigurable Computing Arrays For Efficient CGRA-based Embedded Systems,”  in the preceding of 46th IEEE/ACM Design Automation Conference, San Francisco, California, July 2009 (Acceptance rate 22%).
  4. Yoonjin Kim and Rabi N. Mahapatra, “Dynamic Context Management for Low Power Coarse-Grained Reconfigurable Architecture”, in proc. the 19th IEEE/ACM Great Lake Symposium on VLSI (GLSVLSI 2009), pp. 33-38, May 2009 (Acceptance rate 16%).