1.     Aalap Tripathy*, Atish Patra,* Suneil Mohan*, Rabi Mahapatra, “Designing a Collaborative Filtering Recommender on the Single Chip Cloud Computer”, Proceedings of 3rd International Workshop on Petascale data analytics: challenges & opportunities (PDAC ’12), Nov. 12, 2012, Salt Lake City, UT, USA

2.     N. Gupta* and R. N. Mahapatra, “Power Aware Pfair Scheduling in Multiprocessor Real Time Systems”, Cool Work In Progress session at Design and Automation Conference (DAC), 2011.

3.     Suneil Mohan, Aalap Tripathy, Amitava Biswas and Rabi Mahapatra, “Parallel Processor Core for Semantic Search Engines”, Workshop on Large-Scale Parallel Processing (LSPP) – IEEE International Parallel and Distributed Processing Symposium (IPDPS’11), May 16-20, 2011.

4.     A. Mandal, S. Mandal, A. Trpathy, and R. Mahapatra, “A Bio-inspired Framework for Secure System on Chip,” Proceedings of Workshop on SoC Architecture, Acclerator and Workload, Jan 2010.

5.     S. K. Mandal, N. Gupta, A. Mandal, J. Malave, J. D. Lee and R. Mahapatra, “NoCBench: A Benchmarking Platform for Network on Chip”, In Proceedings of Workshop on Unique Chips and Systems, UCAS 2009.

6.     David Beals, Jason Lee, Rabi Mahapatra and Nikhil Gupta, “Verification of COTS System on Chip for Safety Critical Applications,” to appear in the Proceedings of 10th Workshop on Microprocessor Test and Verification, Austin, December 2009.

7.     H. Yu* and R. Mahapatra, “A Power- and Memory-Efficient Hashing for Packet Processing”, to appear as poster paper in IPDPS 2009.

8.     Y. Kim* and R. Mahapatra, “Reusable Context Pipelining for Low Power Coarse-Grained Reconfigurable Architecture”, Proceedings of 15th Reconfigurable Architecture Workshop, IPDPS 2008, pp.1-8.

9.     J. D. Lee* and R. Mahapatra, “Distributed Test Vector Storage for Safety-Critical NoC-based Systems”, to appear in Proceedings of IEEE Workshop on UCAS-4, 2008.

10.  H. Yu*, R. N. Mahapatra, U. Lee; “Power-saving Hybrid CAMs for Parallel Lookups”, Poster Paper in Proceedings of ICNP 2008, pp.1-2.

11.  Heeyeol Yu*, Rabi Mahapatra, “A Pipelined Indexing Hash Table using Bloom and Fingerprint Filters for IP Lookup”, Poster paper in Proceedings of SIGCOMM 2008, pp.463-464.

12.  J. D. Lee*, P. Bhojwani* and R. Mahapatra, “On-Line Health Monitoring via Statistical Clustering of On-Chip Communication”, Workshop on Diagnostic Services in Network-on-Chips – Test, Debug, and On-Line Monitoring, ACM/IEEE DATE 2007.

13.  S. P. Mohanty, E. Kougianos, and R. Mahapatra, “A Comparative Analysis of Gate Leakage and Performance of High-K Nanoscale CMOS Logic Gates,” in Proceedings of the 16th ACM/IEEE International Workshop on Logic and Synthesis (IWLS), pp. 31-38, 2007.

14.  P. Bhojwani*, R. Singhal*, G.  Choi, R. Mahapatra, “Forward Error Correction for On-chip Interconnection Networks”, Proceedings of International Workshop on Unique Chips and Systems (UCAS-II) 2006.

15.  A. Biswas* and R. Mahapatra,” Managing Confidence and Reliability in Complex Software Systems with an Adaptive System Monitor”, NSF Workshop on High-Confidence Software Platforms for Cyber-Physical Systems (HCSP-CPS), Virginia, Nov 2006.

16.   M. Nolan* and R. Mahapatra, “A TDM Test Scheduling Method for Network-on-Chip Systems,” to be presented in IEEE International Workshop on Microprocessor Verification & Testing (MTV) 2005.

17.  H. Kim*, E. J. Kim and R. Mahapatra, “Power Management in RAID Server Disk System Using Multiple Idle States”, Proceedings of International Workshop on Unique Chips and Systems (UCAS) 2005.

18.  N. Goyal* and R. Mahapatra “Energy Characterization of CRAMFS for Embedded Systems”, International Workshop on Software Support for Portable Storage (IWSSPS), March 2005.

19.  N Subramanian*, Sunil Pandita* and Rabi Mahapatra, “Co-Design of Reactive Embedded System for Motion Control in Hostile Environment”, accepted for presentation in 8th IAPR workshop on Machine Vision Applications, Japan, December 2002. (Acceptance rate 66%)

20.  K. Pramaod* and Rabi Mahapatra, “PAP: Power Aware Partitioning of Reconfigurable Systems”, HPCA Workshop on SSRS, Anaheim, CA, Feb. 8, 2003.

21.   Debashis Mohanty*, Rabi Mahapatra and Gwan Choi, “A Design Space Exploration Framework in Multiprocessor SoC Codesign”, Proceedings of Workshop on RTSS Embedded Systems, Dec 3, 2001.

22.  R. N. Mahapatra and B. K. Kar*, “A Systolic Design of Benes and Data Manipulator Network for VLSI Implementation”, Third Intl. Workshop on VLSI System Design, pp.275-282, Jan.1990

23.   L. K. Dash*, R. N. Mahapatra and B. N. Chatterji, “An Efficient Hardware Scheme for Computing Histogram”, Intl. Seminar on Frontiers in Imaging, Trivandrum, July 1990.

24.   R. N. Mahapatra and J. Majumdar*, “Modeling FCT Algorithm on MBCC Multiprocessors”, Indo-US Workshop, Pune, Dec. 1993.

25.   C. R. Tripathy*, R. N. Mahapatra and R. B. Misra, “Reliability Evaluation of MIN by Network Decomposition”, First Intl. Workshop on Parallel Processing, Bangalore, pp.228-233, Dec. 1994.

26.   B. K. Das*, R. N. Mahapatra and B. N. Chatterji, “Design of Multiprocessor Based Image Tracker”, IEEE Conf. on Microprocessor Application on Industrial Instrumentation Systems, Bhubaneswar, August 1994.

27.   B. K. Das*, R. N. Mahapatra and B. N. Chatterji, “Modeling of Wavelet Transform on Multistage Interconnection Network”, Second Australian Conf. on Parallel and Real-Time Systems, Perth, September 1995.

28.   R. N. Mahapatra, B. K. Das*, V. A. Kumar* and B. N. Chatterji, “Performance of 2D IFCT Algorithm on Multiprocessors”, Proc. Workshop on Parallel Processing, BARC, Bombay, Feb.1990.

29.  C. R. Tripathy*, R. B. Misra and R. N. Mahapatra, “An efficient method to evaluate reliability of multistage interconnection networks”, Proc. Natl. Sem. on Information Technology, Itanagar, India, pp. 1-7, 1993.

Technical Reports

1.       B. Green, J. Marotta, B. Petre, K. Lillestolen, R. Spencer, N. Gupta, D. O’Leary, J. D. Lee, J. Strasburger, A. Nordsieck, B. Manners, and R. N. Mahapatra, “Handbook For The Selection And Evaluation Of Microprocessors For Airborne Systems”, Federal Aviation Administration report DOT/FAA/AR-11/2, 2011.

2.       Biswas, A., Mohan, S., Panigrahy, J., Mahapatra, R., “Intelligent Semantic Technologies for Distributed Search Networks”, Technical Report, Department of Computer Science, Texas A&M University, US, July 2008

3.       John Wisinger* and Rabi Mahapatra, “FPGA Based Image Processing with the Curvelet Transform”, Technical Report # TR-CS-2003-01-0

4.       Rabi N Mahapatra and Brian Murray*, “GEARS: Graphics Embedded Accelerated Rendering Systems: Development of an Embedded 3D Graphic Processor”, Technical Report # TR-CS-2002-05-1

5.       Vinod Raman* Pankaj Bhagwat* and Rabi Mahapatra, “An Efficient Implementation of IS-95 CDMA Reverse Link Transceiver: A Codesign Approach”, TR# TR-CS-2002-05-2

6.       Rajesh Prathipati* and Rabi Mahapatra, “A Three Step Approach For Low Power Static Scheduling Of Real-Time Embedded Systems” Technical Report # TR-CS-2002-06-0

7.       Di Wu* and Rabi Mahapatra, “Multiprocessor Based Voltage Scaling: A Low-Power Technique”, Technical Report # TR-CS-2002-06-1

8.       Raman Senthil Kumar*, Bhamy Madhava Shenoy* and Rabi Mahapatra, “Optimizing Power at the Physical Layer in a Wireless Ad Hoc Network”, TR# TR-CS-2002-06-2

9.       Narayanan Swaminathan* and Rabi Mahapatra, “Communication Architecture Synthesis of Packet-Switched Network-on-Chip”, Technical Report # TR-CS-2002-08-0

10.    Sunil Bhosekar* and Rabi Mahapatra, “Estimating Cache & TLB Power in Embedded Processor Using Complete Machine Simulation”, Technical Report # TR-CS-2001-08-0