CONTACT:RABI@CSE.TAMU.EDU
 

Journals

1. Amar Rasheed*, Rabi N. Mahapatra: The Three-Tier Security Scheme in Wireless Sensor Networks with Mobile Sinks. IEEE Trans. Parallel Distrib. Syst. 23(5): 958-965 (2012)

2. Heeyeol Yu*, Rabi N. Mahapatra: A Power and Throughput-Efficient Packet Classifier with n Bloom Filters. IEEE Trans. Computers 60(8): 1182-1193 (2011

3. Amar Rasheed*, Rabi N. Mahapatra: Key Predistribution Schemes for Establishing Pairwise Keys with a Mobile Sink in Sensor Networks. IEEE Trans. Parallel Distrib. Syst. 22(1): 176-184 (2011)

4. Suman K Mandal*, Rabi N. Mahapatra, Praveen Bhojwani*, Saraju P. Mohanty: IntellBatt: Toward a Smarter Battery. IEEE Computer 43(3): 67-71 (2010)

5. Suman K Mandal*, Rabi N. Mahapatra: PowerAntz: Ant behavior inspired power budget distribution scheme for Network-on-Chip systems. Microelectronics Journal 41(8): 523-531 (2010)

6. Y. Kim*, R. Mahapatra and K. Choi, “Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture,” IEEE Transactions on VLSI Systems, 18(10) 2010, pp. 1471-1482.

7. Y. Kim* and R. Mahapatra, “Dynamic Context Compression for Low Power Coarse-Grained Reconfigurable Architecture,” IEEE Transaction on VLSI Systems, 18(1), 2010, pp.15-28.

8. Y. Kim*, R. Mahapatra, I. Park, and K. Choi, “Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture,” IEEE Transactions on VLSI, Systems 17(5), 2009, pp. 593-603.

9. D. Dechev, R. Mahapatra and B. Stroustrup, “Practical and Verifiable C++ Dynamic cast in Autonomous Space Systems”, Special Issue on Real-time Distributed Computing and Ubiquitous computing in Memory – Intl. Journal of Computing Science and Engineering (JCSE), December 2008.

10. Singhal, R*.; Gwan Choi; Mahapatra, R.N.; “Data Handling Limits of On-Chip Interconnects”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 16,  Issue 6,  June 2008 Page(s):707 – 713

11. Bhojwani, P.S*.; Mahapatra, R.N.; “Robust Concurrent Online Testing of Network-on-Chip-Based SoCs “,IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 16,  Issue 9,  Sept. 2008 Page(s):1199 – 1209

12. Subrata Acharya*, Rabi N. Mahapatra: A Dynamic Slack Management Technique for Real-Time Distributed Embedded Systems. IEEE Trans. Computers 57(2): 215-230 (2008)

13. John Mark Nolen*, Rabi N. Mahapatra: Time-Division-Multiplexed Test Delivery for NoC Systems. IEEE Design & Test of Computers 25(1): 44-51 (2008)

14. S. P Mohanty, E. Kougianos and R. Mahapatra, “Hardware Assisted Watermarking for Multimedia,” Special Issue on Circuits and Systems for Real-Time Security and Copyright Protection of Multimedia, Intl Journal of Computers and Electrical Engineering (Elsevier Ltd.), accepted for publication.

15. Seraj Ahmad, Rabi N. Mahapatra: An Efficient Approach to On-Chip Logic Minimization. IEEE Trans. VLSI Syst. 15(9): 1040-1050 (2007)

16. D. Wu*, J. Hu and R. Mahapatra, “Antenna Avoidance in Layer Assignment”, IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 734-738 (2006).

17. A. Rajaram*, J. Hu, R. Mahapatra, “Reducing Clock Skew Variability via Cross Links”, IEEE Transactions on CAD, 25(6), 1176-1182 (2006)

18. A. Rajaram*, J. Hu, W. Guo, R. Mahapatra and B. Lu, “Analytical Bound for Unwanted Clock Skew Due to Wire Width Variation,” IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1869-1876 (2006).

19. Vijay Kappagantula*, Subrata Acharya* and Rabi N Mahapatra, “A partitioning Algorithm for Power Constrained Reconfigurable Real-Time System”, Microprocessors and Microsystems Journal. (Accepted).

20. R. Mahapatra and W. Zhao., “An Energy efficient Slack Distribution Technique for Multimode Distributed Real-time embedded Systems”, IEEE Transactions on Parallel and Distributed Systems Volume 16, Issue 7, July 2005 pp.650 – 662.

21. V. C. Ravikumar*, R. Mahapatra and L. N Bhuyan, “EaseCAM: An Energy and Storage Efficient TCAM-based Router Architecture”, IEEE Transactions on Computers, Vol.54, No.5, May 2005 pp.521-533.

22. A. Kumar and R. Mahapatra “An Integrated Scheduling and Buffer Management Scheme for Input Queued Switches with Finite Buffer Space”, Computers and Communication Journal, Elsevier Publications, Volume 29, Issue 1, 2005, pp. 42-51.

23. Ravikumar V C*, and Rabi N Mahapatra, “Ternary-CAM Architecture for IP Lookup Using Prefix Properties”, IEEE Micro, April/May 2004, pp.60-69.

24. S. Mahapatra* and Rabi Mahapatra, “Mapping of Neural Net Models onto Systolic Arrays”, Journal of Parallel and Distributed Computing”, Vol. 60, 2000, pp. 677-689.

25. S. Mahapatra*, R. N. Mahapatra and B. N. Chatterji, “Mapping of Neural Net Models onto Massively Parallel Hierarchical Computer Systems”, Journal of System Architecture”, Vol. 45, No. 11, May 1999, pp. 919-929.

26. Ashis Pani*, G. P. Bhattacharjee and R. N. Mahapatra “Event Scheduling using Allen Algebra”, Intl. Journal of Computer Mathematics (ICJM), Vol. 70, pp. 87-97, 1998.

27. R. N. Mahapatra, A. Kumar* and B. N. Chatterji, “Performance Analysis of 2-D Inverse Fast Cosine Transform Employing Multiprocessors”, IEEE Transaction on Signal Processing, Vol.45, No.5, May’97, pp.1323 – 1335.

28. B. K. Das*, R. N. Mahapatra and B. N. Chatterji, “Modeling Hadamard Haar Transform Algorithm for Omega Connected Multiprocessor”, Signal Processing, Elsevier Publishers, Vol.58, No. 3, May 1997, pp.293 – 301.

29. S. Mahapatra*, R. N. Mahapatra and B. N. Chatterji, “A Parallel formulation of Back Propagation learning on Distributed Memory Multiprocessors”, Parallel Computing, Vol., No.12, Feb. 1997, pp.1661-1675.

30. R. N. Mahapatra and S. Mahapatra*, “Mapping Neural Network Models onto Two-Dimensional Processor Arrays”, Parallel Computing Journal, Vol. 22, No. 10, Jan. 1997, pp. 1345-1357.

31. C. R. Tripathy*, R. N. Mahapatra and R. B. Misra, “Reliability Analysis of Hypercube Multicomputers”, Microelectronics and Reliability, Vol. 37 (6), 1997, pp. 885-891.

32. C. R. Tripathy*, S. Patra*, R. B. Misra and R. N. Mahapatra, Reliability Evaluation of  Multistage Interconnection Networks with Multistate Elements”, Microelectronics and Reliability, Vol. 36, No.3, 1996, pp.423-428.

33. B. K. Das*, R. N. Mahapatra and B. N. Chatterji, “Performance Modeling of Discrete Cosine Transform for Star-Graph Connected Multiprocessors”, Intl. Journal of Circuits Systems and Computers, Vol. 6, No.6, 1996, pp. 635-648

34. C.R. Tripathy*, R. N. Mahapatra and R. B. Misra, “Fuzzy Reliability Evaluation of Multistage Interconnection Network”, Computer science and Information, Vol. 25, No. 4, Dec. 1995, pp.17-29.

35. R. N. Mahapatra and Sudipta Mahapatra*, “Modeling 2-D IFCT Algorithm on a Multistage Interconnection Network”, Signal Processing, Vol. 30, No.2, 1993, pp. 235-243.

36. R. N. Mahapatra and H. Pareek*, “Modeling a Fast Parallel Thinning Algorithm for Shared Memory SIMD Computers”, Information Processing Letters, Vol. 40, No. 5, Dec. 1991, pp.257-261.

37. A. Dutta*, S.V. Joshi* and R. N. Mahapatra, “Modeling Morphological Thinning Algorithm for Shared Memory SIMD Computers”, Parallel Processing Letters, Vol. 1, No.1, 1991, pp.59-65.

38. R. N. Mahapatra, “Microprocessor Implementation of Fast Convolver”, IETE Technical Review, Vol.5, No.5, Aug. 1988, pp.326-328.